1. Field of the invention
The present invention pertains generally to calibrating dual ramp interpolators used to produce precise delays.
2. Description of the Background
Voltage-to-time converters have been used for measuring the duration between two events. One form of a voltage-to-time converter is the single ramp interpolator. The single ramp interpolator measures durations by accumulating charge on a capacitor from a current source. The resulting voltage is proportional to the duration. For example, one volt may be equal to one microsecond, so 10 volts would be a 10 microsecond delay. The single ramp interpolator has limitations. The amount of delay which can be controlled on a single ramp interpolator is limited by the amount of voltage which can be generated on the capacitor. The single ramp interpolator cannot be used for long delays. Also, the accuracy of the single ramp interpolator is limited by the component tolerances chosen in the design and manufacture of the single ramp interpolator.
A dual ramp interpolator eliminates the problem of the time limitation by providing a clock in conjunction with a voltage-to-time converter. In this way, long periods of duration can be measured. The duration is only limited by the largest number which can be represented by the counter that counts the clock cycles. The clock is used to measure, usually, the majority of the duration with the interpolator interpolating durations which happen in-between clock cycles. For example, an event which occurs one-third of the way through a clock cycle, the clock will only begin to count at the next clock cycle. As much as two-thirds of a clock cycle will be lost in the duration. Sometimes, clocks can begin counting at either the rise pulse or the fall pulse, so the loss would be one-half minus one-third which is equal to one-sixth of a clock cycle.
By putting an interpolator with the clock, this uncertainty is avoided. The interpolator will effectively measure the fraction of a clock cycle.
Often, what is needed is not a precise measurement of the duration between two events, but a predetermined duration between two events. The first event can happen at any time, but the second event is controlled to happen only after a predetermined time from the first event. The single ramp interpolator with a clock can measure reasonably precisely the duration between two events, but cannot control the duration to a predetermined time period. A second ramp interpolator is required. If the predetermined duration is five clock cycles and the first event happens three-fourths of the way through a clock cycle then another four and three-fourths of a clock cycle must be added onto the one-fourth in order to obtain the required five clock cycle delay. The clock can count out the four clock cycles, but a second ramp interpolator must be used to count the three-fourths of a clock cycle.
Instead of using two separate interpolators, a dual ramp interpolator can be used. The dual ramp interpolator interpolates the first fraction of a clock cycle, then holds the resulting voltage at a clock pulse while the clock cycles through an integral number of cycles, and then interpolates another fraction of a clock cycle by ramping to a preselected voltage. When the dual ramp interpolator reaches the preselected voltage then the duration is determined. The preselected voltage should be equivalent to at least one clock cycle, otherwise the interpolator could time-out before reaching the predetermined delay. For example the delay could be chosen to be 5.5 clock cycles, with the clock counting 4.0 cycles and the interpolator counting 1.5 cycles. The 1.5 clock cycles will be split up differently depending on when the first event occurs, but the total ramp time of the dual ramps will always equal 1.5 clock cycles. If the first ramp is 0.9 clock cycles then the second ramp will be 0.6 clock cycles.
Sometimes, the exact interpolator delay is not so important as knowing that the delay will be the same from one series of events to another series of events. For instance, if the delay is 1.7 clock cycles instead of 1.5, but the delay is always 1.7 clock cycles, then this would be satisfactory. It would also be satisfactory if the delay was unknown, but always the same.
The problem is how to vary the delay by a known amount. A common method is to vary the delay by an integral clock cycle or by a clock pulse. The smallest incremental delay change would be one-half of a clock cycle. No other multiples of a fraction less than one would be permissible.
Another way is to vary the preselected voltage at which the second ramp completes the duration. Typically, when this is done, parameters of the components and design are critical. The calibration is achieved by knowing precisely the capacitance(C) of the capacitor, the current of the current source, and the voltage on the capacitor. The time, t is then given by t=V*C/I, and the incremental delay, delta t, is given by delta t=delta V*C/I. In a manufacturing environment, where many of these converters are to be built, controlling or measuring each component is expensive and time consuming. Also, component values can change depending on the ambient conditions of temperature, barometric pressure, and humidity. The component values must be controlled, known, or measured for various conditions in order to maintain calibration.
A calibration method is needed which can use components which have wide tolerances and it is not necessary to take the time to know or measure the precise parameter values of the components, yet be able to control the delay accurately.